Wu, Yu-Ting, Chaomin Luo, Mohan Krishnan, and Mark Paulik
VLSI circuit floorplanning is becoming increasingly important as a tool to VLSI design flows in the hierarchical design. VLSI circuit floorplanning attempts to pack all the modules within a given floorplan outline, and aims to simultaneously minimize wirelength, area and overlap, and possibly also timing. Computational intelligence models play an important role in state-of-the-art hierarchical methods to multi-level design of large scale ASICs and SoCs. The VLSI circuit floorplan optimization problem is an important problem in VLSI design. A set of rectangular blocks is given and the objective is to find a rectangle with minimum area that encloses all blocks. In this project, a simulated annealing approach integrated with a fuzzy logic scheme for VLSI floorplanning design is proposed. The test results in terms of MCNC Circuit Benchmark demonstrate the proposed fuzzy-annealing VLSI circuit floorplanning model outperforms over other floorplanning models. The total wirelength of VLSI circuit is successfully minimized in MCNC Circuit Benchmark.